1. Technical Field
This invention relates to a method of virtualizing hardware resources in a multiprocessor computing environment. More specifically, the invention relates to a method and system for dynamically remapping resources through platform firmware.
2. Description of the Prior Art
In a computing environment, cache memory may serve as a method for providing fast access to recently used portions of a program's code and data. Similarly, the main memory in a computing environment can act as a cache for secondary storage, such as that implemented with magnetic disks. Virtual memory manages the two levels of memory hierarchy represented by the main memory and secondary storage. The virtual memory allows for both efficient sharing of memory among multiple programs and removes the programming burdens represented by a limited fixed amount of main memory. Both the translation of each program's address space and the protection of the address space from other programs are provided by virtual memory hardware. Accordingly, the CPU produces a virtual memory address which is translated by a combination of hardware and software to a physical memory address, which in turn can be used to access main memory, which is also known as memory mapping.
FIG. 1 is a block diagram 10 illustrating the use of virtual memory management of the prior art. The CPU has a plurality of virtual memory addresses 20 used by the operating system and/OT application software 23. The virtual address 20 is translated into a physical address 30 through a page table look-up 25. The physical address 30 drives memory decode logic 35 to access the appropriate memory resources 40a-40d. The memory decode logic (e.g. motherboard chipset), while possibly configurable at boot time (e.g. by BIOS), is static in that it does not change at runtime. For example, for a given address, the memory decode logic always selects the same memory device. Accordingly, the page look-up table 25 translates the virtual address of the CPU to a physical memory address under the direction of the operating system 27.
FIG. 2 is a block diagram 45 illustrating the use of I/O addressing in the prior art. The CPU has a plurality of I/O addresses 50, which are assigned to I/O resources 60a-60d at boot time. The CPU I/O address 50 drives I/O decode logic 55 to access the appropriate I/O resource 60a-60d. The I/O decode logic 55 (e.g. motherboard chipset), while possibly being configurable at boot time (e.g. by BIOS), is static in that it does not change at runtime. In some cases, a physical I/O resource may be removed or installed after boot, but the I/O addresses assigned to a given resource is not changed once installed. Accordingly, the prior art I/O addressing is static throughout operation of the system.
Multiprocessor systems contain multiple processors (also referred to herein as “CPUs”) that can execute multiple processes or multiple threads within a single process simultaneously in a manner known as parallel computing. In general, multiprocessor systems execute multiple processes or threads faster than conventional single processor systems, such as personal computers, that execute only one thread at a time. Shared memory multiprocessor systems offer a common physical memory address space that all processors can access. Multiple processes therein, or multiple threads within a process, can communicate through shared variables in memory.
Many multiprocessor systems are constructed of a plurality of computational nodes (also known as “building blocks” or “quads”), which can be joined together by system interconnect hardware to form one or more independent computing environments, such environments being known as partitions. At boot time, the firmware of an interconnected computer system configures the system interconnect, assigning addresses to the system's processors, memory, and I/O devices. These address assignments are fixed, each device remaining at a constant address until the system is powered off or rebooted. All these fixed addresses, known collectively as the system's memory and I/O resource maps, are visible to the system's software, and the correct operation of the system depends on the resources being accessible at those fixed addresses.
It is often desirable to change the organization of an interconnected system in response to changing workload or the need to remove hardware for servicing. Further, it is often desirable to divide a lightly loaded partition such that the currently running operating system continues to function, with fewer resources, and the formerly underutilized nodes form a new, independent partition available for other work. However, when a partition is divided, the fixed address resources required by the currently running operating system may include I/O resources located on the nodes being removed. Accordingly, it is desirable to be able to change the I/O resource map at run time so that the fixed addresses known to the operating system may be re-assigned to different nodes at different times.